
Exerpt from "De Re Intellivision"

Compilation by William M. Moeller


                      
General instrument CP160 processor overview 


The CPU is the General Instruments CP1610. This is a general purpose
16-bit microprocessor which has 1024 separate op-codes, and can equally
well use 8-bit, 10-bit, 14-bit, and 16-bit RAM or ROM. The CP1610 in the
Intellivision uses a machine cycle rate of 894.886 KHz. Individual
operations on the 1610 take between 4 and 12 microcycles (Note: the
CP1600 is the prototypical or conventional form of the microprocessor,
the CP1610 used in the Intellivision is precisely the same in all
respects except for a differing clock rate.)

Since most 1610 instructions are 10-bits wide, game programs are stored
in 10-bit wide ROMs. This 10-bit "byte" is referred to as a decle
(rhymes with "heckle"). Some instructions require 16 bits; these are
stored in two successive 10-bit locations, referred to as a bidecle.
(For prototyping, dual 8-bit EPROMs are used, with the low 8 bits of
each decle stored in one EPROM and the top 2 bits stored in the other.)

* Data and addresses are multiplexed on a single 16 bit bus.

* Ouput buffered via internal line drivers.

* 8 Bus phases (read/write/waitstate/DMA/ etc)

* Branch on external condition (16 conditions supported)

* Standard compliment of status flags. (S,Z,C,O)  Typical polarity.

CP-1600 Register set 


 8 bits 8 bits
ĿĿ

Ŀ R0  No assigned function.
Ĵ R1 Ŀ
Ĵ R2   Data Counters
Ĵ R3  
Ĵ R4  Data Counters
Ĵ R5   with autoincrement
Ĵ R6  Stack
Ĵ R7  Program Counter



    16 bits


* All 8 registers can be referenced as general purpose registers.

* All registers with the exception of R0 have unique features shared
  with the other registers in their class.

* JSR moves the current program counter into a register.

* Addressing modes... Direct. Implied. Stack

* CPU STACK 112 words, mapped from 002F0H-0035FH.


CP1600 Instruction set 

                                                 mmm = data counter reg
            10 bit Instruction                   mmm = 000 = R0
              Ŀ                           001 = R1
HLT            0000 000 000                            010 = R2
SDBD           0000 000 001                            011 = R3
EIS            0000 000 010                            100 = R4
DIS            0000 000 011                            101 = R5
JD    LABEL    0000 000 100 11pppppp01 pppp            110 = R6
J     LABEL    0000 000 100 11pppppp10 pppp            111 = R7
JSR   RB,LABEL 0000 000 100 bbpppppp00 pppp
JSRE  RB,LABEL 0000 000 100 bbpppppp01 pppp      m = shift count
JSRD  RB,LABEL 0000 000 100 bbpppppp10 pppp
TCI            0000 000 101                      p = one bit of
CLRC           0000 000 110                          immediate address
SETC           0000 000 111
INCR  RD       0000 001 ddd                      rr = 00 = R0
DECR  RD       0000 010 ddd                           01 = R1
COMR  RD       0000 011 ddd                           10 = R2
NEGR  RD       0000 100 ddd                           11 = R3
ADCR  RD       0000 101 ddd
GSWD  RR       0000 110 0rr                      sss = source register
NOP   (2)      0000 110 10m                      sss = 000 = R0
SIN   (2)      0000 110 11m                            001 = R1
RSWD  RS       0000 111 sss                            010 = R2
                                                       011 = R3
SWAP  RR(,2)   0001 000 mrr                            100 = R4
SLL   RR(,2)   0001 001 mrr                            101 = R5
SLLC  RR(,2)   0001 011 mrr                            110 = R6
RLC   RR(,2)   0001 010 mrr                            111 = R7
SLR   RR(,2)   0001 100 mrr
RRC   RR(,2)   0001 110 mrr                      s = Sign of
SAR   RR(,2)   0001 1c1 mrr                          displacement
SARC  RR(,2)   0001 111 mrr                          1 = negative

TSTR  RS       0010 sss sss                      bb = One of three regs
MOVR  RS,RD    0010 sss ddd                      bb = 00 = R0
JR    RS       0010 sss 111                           01 = R1
                                                      10 = R2
ADDR  RS,RD    0011 sss ddd
                                                 eeee = 4 bit branch
SUBR  RS,RD    0100 sss ddd                             condition external
CMPR  RS,RD    0101 sss ddd                             lines bext0-4
ANDR  RS,RD    0110 sss ddd
XORR  RS,RD    0111 sss ddd                      ddd = Destination reg
CLRR  RD       0111 ddd ddd                      ddd = 000 = R0
                                                       001 = R1
B     DISP     1000 z00 000 pppp                       010 = R2
NOPP           1000 z01 000 pppp                       011 = R3
BCOND DISP,E   1000 z0c ccc pppp                       100 = R4
BEXT  DISP,E   1000 z1e eee pppp                       101 = R5
                                                       110 = R6
MVO   RS,ADDR  1001 000 sss pppp                       111 = R78
MVO@  RS,RM    1001 mmm sss
PSHR  RS       1001 110 sss                      cccc = 4 bit branch
MVOI  RS,DATA  1001 111 sss ||||                        condition

MVI   ADDR,RD  1010 000 ddd pppp                 |||| = one word of
MVI'  RM,RD    1010 mmm ddd                             immediate data
PULR  RD       1010 110 ddd                             (10 or 16 bits)
MVI   DATA,RD  1010 111 ddd ||||

ADD   ADDR,RD  1011 000 ddd pppp       Branch conditons 
ADD@  RM,RD    1011 mmm ddd            
ADDI  DATA,RD  1011 111 ddd ||||       0001  Carry / Greater than
                                       1001  No Carry / Less than
SUB   ADDR,RD  1100 000 ddd pppp       0010  Overflow
SUB@  RM,RD    1100 mmm ddd            1010  No overflow
SUBT  DATA,RD  1100 111 ddd ||||       0011  Positive
                                       0100  Negative
CMP   ADDR,RS  1101 000 sss pppp       0100  equal (zero)
CMP@  RM,RS    1101 mmm sss            1100  Not equal (not zero)
CMPI  DATA,RS  1101 111 sss |||        0101  Less than
                                       1101  Greater than or equal
AND   ADDR,RD  1110 000 ddd pppp       0110  Less than or equal
AND@  RM,RD    1110 mmm ddd            1110  Greater than
ANDI  DATA,RD  1110 111 ddd ||||       0111  Unequal sign and carry
                                       1111  Equal sign and carry
XOR   ADDR,RD  1111 000 ddd pppp
XOR@  RM,RD    1111 mmm ddd
XORI  DATA,RD  1111 111 ddd ||||


Instruction Set (Summary Listing) 


INTERNAL REFERENCE INSTRUCTIONS

Ŀ
Register To Register 
Ŀ
Mnemonics          Operation          Microcycles      Comments             
Ĵ
 MOVR     MOVe Register                 6/7                              
Ĵ
 TSTR     TeST Register                 6/7    MOVR to itself            
Ĵ
 JR       Jump to address in Register    7     MOVR to PC                
Ĵ
 ADDR     ADD contents of Registers      6                               
Ĵ
 SUBR     SUBtract contents of Registers 6                               
Ĵ
 CMPR     CoMPare Registers by subtr.    6    Results not stored         
Ĵ
 ANDR     logical AND Registers          6                               
Ĵ
 XORR     eXclusive OR Registers         6                               
Ĵ
 CLRR     CLeaR Register                 6    XORR with itself           


                                                                   
Ŀ
Single Register      
Ŀ
Mnemonics          Operation          Microcycles      Comments             
Ĵ
 INCR     INCrement Register             6                               
Ĵ
 DECR     DECrement Register             6                               
Ĵ
 COMR     COMplement Register            6     One's Complement          
Ĵ
 NEGR     NEGate Register                6     Two's Complement          
Ĵ
 ADCR     ADd Carry Bit to Register      6                               
Ĵ
 GSWD     Get Status WorD                6                               
Ĵ
 NOP      No OPeration                   6                               
Ĵ
 SIN      Software INterrupt             6     Pulse to PCIT pin         
Ĵ
 RSWD     Return Status WorD             6                               


                                                   
Ŀ
Register Shift       
Ŀ
Mnemonics          Operation          Microcycles      Comments             
Ĵ
 SWAP     SWAP 8-bit bytes               6    Ŀ                       
Ĵ                            
 SLL      Shift Logical Left             6                              
Ĵ                            
 RLC      Rotate Left thru Carry         6          Not interruptable   
Ĵ       One or two position  
 SLLC     Shift Logical Left thru Carry  6          shift capability.   
Ĵ      Two position SWAP   
 SLR      Shift Logical Right            6           not supported      
Ĵ                            
 SAR      Shift Arithmetic Right         5          (Add two cycles for 
Ĵ         2-position shift)  
 RRC      Rotate Right thru Carry        6                              
Ĵ                            
 SARC     Shift Arithmetic Right thru    6                           
          Carry                                                          


                                                             
Ŀ
Control Instructions 
Ŀ
Mnemonics          Operation          Microcycles      Comments             
Ĵ
 HLT      HaLT                           4                               
Ĵ
 SDBD     Set Double Byte Data           4   Must precede external       
reference to double byteĴ
 EIS      Enable Interrupt System        4    Ŀ    data                
Ĵ                            
 DIS      Disable Interrupt System       4                              
Ĵ                            
 TCI      Terminate Current Interrupt    4        Not interruptable    
 Ĵ                            
 CLRC     CLeaR Carry to zero            4                              
Ĵ                            
 SETC     SET Carry to one               4                            



Ŀ
Jump Instructions    
Ŀ
Mnemonics          Operation          Microcycles      Comments             
Ĵ
 J        Jump                           12                              
Ĵ
 JE       Jump, Enable, interrupt        12                              
Ĵ
 JD       Jump, Disable interrupt        12                              
Ĵ
 JSR      Jump, Save Return              12   Ŀ                        
Ĵ                            
 JSRE     Jump, Save Return & Enable     12       Return Address      
Ĵ         saved in R4,       
 JSRD     Jump, Save Return & Disable    12            5 or 6           
          interrupt                                                   




EXTERNAL REFERENCE INSTRUCTIONS
                                       Note:
Ŀ    Add 2 cycles if test condition is
Conditional Branch Instructions      true except "*"
Ŀ
Mnemonics          Operation          Microcycles      Comments              
Ĵ
 B         unconditional Branch           9*                              
Ĵ
 NOPP      NO OPeration                   7*    Two words                 
Ĵ
 BC(BLGE)  Branch on Carry                7     C = 1                     
Ĵ
 BNC       Branch on No Carry             7     C = 0                     
Ĵ
 BOV       Branch on OVerflow             7     OV = 1                    
Ĵ
 BNOV      Branch on No OVerflow          7     OV = 0                    
Ĵ
 BPL       Branch on PLus                 7     S = 0                     
Ĵ
 BMI       Branch on Minus                7     S = 1                     
Ĵ
 BZE(BEQ) Branch if Not Zero or Not EQual 7     Z = 1                     
Ĵ
BNZE(BNEQ)Branch if Not Zero or Not EQual 7     Z = 0                     
Ĵ
 BLT       Branch if Less Than            7     SVOV = 1                  
Ĵ
 BGE      Branch if Greater than or Equal 7     SVOV = 0                  
Ĵ
 BLE       Branch if Less than or Equal   7     ZV(SVOV) = 1              
Ĵ
 BGT       Branch if Greater Than         7     ZV(SVOV) = 0              
Ĵ
 BUSC      Branch if Sign not = Carry     7     CVS = 1                   
Ĵ
 BESC      Branch if Sign = Carry         7     CVS = 0                   
Ĵ
          Branch if External condition is      LSB of instruction are     
 BEXT                   True              7    decoded select 1 of 16     
                                               external conditions        

                                                                               
Ŀ
  Input/Output       
Ŀ
Mnemonics     Operation               Microcycles            Comments       
Ĵ
                                 Dir.Imm.Indir.Stack                   
Ĵ
 MVO      MoVe Out               11   9   9     9   Not interruptable 
Ĵ
 PSHR     PuSH Register to Stack  -  -    -     9   PSHR=MVO@R6       
                                                    Not interruptable 
Ĵ
 MVI      MoVe in                10   8   8    11                     
Ĵ
 PULR     PULl from stack to      -   -   -    11   PULR-MV1@R6       
              Register                                                
 


Ŀ
  Arithmetic & Logic 
Ŀ
Mnemonics     Operation               Microcycles            Comments       
Ĵ
                                 Dir.Imm.Indir.Stack                   
Ĵ
 ADD      ADD                    10   8   8    11                     
Ĵ
 SUB      SUBtract               10   8   8    11                     
Ĵ
 CMP      CoMPare                10   8   8    11   Result not saved  
Ĵ
 AND      logical AND            10   8   8    11                     
Ĵ
 XOR      eXclusive OR           10   8   8    11                     


NOTE: 1 MICROCYCLE = 2 CLOCK CYCLES

