#
# 68k_test_14
#
# fourteenth test file for the 68k core testing program
#
# tests shift/rotate instructions
#

# $Id$

#
# NOTE: Someone plays fast and loose with flags...
#

#
# FIXME: currently only tests with immediate shift count, should test with
# register shift count (and count of 0) (doublecheck 0 count case flags)
#

#
# FIXME: currently only tests register versions, should test memory versions
#

#
# Test LSL instruction (LSL.B)
#

# test LSL.B
start lsl.b #1, d0 (0xe308), take 1
set mem 0x002000 = 0xe308
set reg d0 = 0x55aa5500
set pc 0x002000
set cycles 8
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0004
check reg d0 = 0x55aa5500
done

# test LSL.B
start lsl.b #1, d0 (0xe308), take 2
set mem 0x002000 = 0xe308
set reg d0 = 0x55aa55aa
set pc 0x002000
set cycles 8
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0011
check reg d0 = 0x55aa5554
done

# test LSL.B
start lsl.b #2, d0 (0xe508), take 1
set mem 0x002000 = 0xe508
set reg d0 = 0x55aa55aa
set pc 0x002000
set cycles 10
set flags 0x0010
run
check cycles 0
check pc 0x002002
check flags 0x0008
check reg d0 = 0x55aa55a8
done

# test LSL.B
start lsl.b d1, d0 (0xe328), take 1
set mem 0x002000 = 0xe328
set reg d0 = 0x55aa55aa
set reg d1 = 0
set pc 0x002000
set cycles 6
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0018
check reg d0 = 0x55aa55aa
done

# test LSL.B
start lsl.b d1, d0 (0xe328), take 2
set mem 0x002000 = 0xe328
set reg d0 = 0x55aa55aa
set reg d1 = 2
set pc 0x002000
set cycles 10
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0008
check reg d0 = 0x55aa55a8
done

#
# Test LSL instruction (LSL.W)
#

# test LSL.W
start lsl.w #1, d0 (0xe348), take 1
set mem 0x002000 = 0xe348
set reg d0 = 0x55aa0000
set pc 0x002000
set cycles 8
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0004
check reg d0 = 0x55aa0000
done

# test LSL.W
start lsl.w #1, d0 (0xe348), take 2
set mem 0x002000 = 0xe348
set reg d0 = 0x55aaaa55
set pc 0x002000
set cycles 8
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0011
check reg d0 = 0x55aa54aa
done

# test LSL.W
start lsl.w #2, d0 (0xe548), take 1
set mem 0x002000 = 0xe548
set reg d0 = 0x55aaaa55
set pc 0x002000
set cycles 10
set flags 0x0010
run
check cycles 0
check pc 0x002002
check flags 0x0008
check reg d0 = 0x55aaa954
done

# test LSL.W
start lsl.w d1, d0 (0xe368), take 1
set mem 0x002000 = 0xe368
set reg d0 = 0x55aa55aa
set reg d1 = 0
set pc 0x002000
set cycles 6
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0010
check reg d0 = 0x55aa55aa
done

# test LSL.W
start lsl.w d1, d0 (0xe368), take 2
set mem 0x002000 = 0xe368
set reg d0 = 0x55aa55aa
set reg d1 = 2
set pc 0x002000
set cycles 10
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0011
check reg d0 = 0x55aa56a8
done

#
# Test LSL instruction (LSL.L)
#

# test LSL.L
start lsl.l #1, d0 (0xe380), take 1
set mem 0x002000 = 0xe380
set reg d0 = 0x00000000
set pc 0x002000
set cycles 10
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0004
check reg d0 = 0x00000000
done

# test LSL.L
start lsl.l #1, d0 (0xe380), take 2
set mem 0x002000 = 0xe380
set reg d0 = 0xd5aaaa55
set pc 0x002000
set cycles 10
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0019
check reg d0 = 0xab5554aa
done

# test LSL.L
start lsl.l #2, d0 (0xe580), take 1
set mem 0x002000 = 0xe580
set reg d0 = 0x15aaaa55
set pc 0x002000
set cycles 12
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0000
check reg d0 = 0x56aaa954
done

# test LSL.L
start lsl.l d1, d0 (0xe3a8), take 1
set mem 0x002000 = 0xe3a8
set reg d0 = 0x55aa55aa
set reg d1 = 0
set pc 0x002000
set cycles 8
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0010
check reg d0 = 0x55aa55aa
done

# test LSL.L
start lsl.l d1, d0 (0xe3a8), take 2
set mem 0x002000 = 0xe3a8
set reg d0 = 0x55aa55aa
set reg d1 = 2
set pc 0x002000
set cycles 12
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0011
check reg d0 = 0x56a956a8
done

#
# Test LSR instruction (LSR.B)
#

# test LSR.B
start lsr.b #1, d0 (0xe208), take 1
set mem 0x002000 = 0xe208
set reg d0 = 0x55aa5500
set pc 0x002000
set cycles 8
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0004
check reg d0 = 0x55aa5500
done

# test LSR.B
start lsr.b #1, d0 (0xe208), take 2
set mem 0x002000 = 0xe208
set reg d0 = 0x55aa55a5
set pc 0x002000
set cycles 8
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0011
check reg d0 = 0x55aa5552
done

# test LSR.B
start lsr.b #2, d0 (0xe408), take 1
set mem 0x002000 = 0xe408
set reg d0 = 0x55aa55a5
set pc 0x002000
set cycles 10
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0000
check reg d0 = 0x55aa5529
done

#
# Test LSR instruction (LSR.W)
#

# test LSR.W
start lsr.w #1, d0 (0xe248), take 1
set mem 0x002000 = 0xe248
set reg d0 = 0x55aa0000
set pc 0x002000
set cycles 8
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0004
check reg d0 = 0x55aa0000
done

# test LSR.W
start lsr.w #1, d0 (0xe248), take 2
set mem 0x002000 = 0xe248
set reg d0 = 0x55aaaa55
set pc 0x002000
set cycles 8
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0011
check reg d0 = 0x55aa552a
done

# test LSR.W
start lsr.w #2, d0 (0xe448), take 1
set mem 0x002000 = 0xe448
set reg d0 = 0x55aaaa54
set pc 0x002000
set cycles 10
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0000
check reg d0 = 0x55aa2a95
done

#
# Test LSR instruction (LSR.L)
#

# test LSR.L
start lsr.l #1, d0 (0xe288), take 1
set mem 0x002000 = 0xe288
set reg d0 = 0x00000000
set pc 0x002000
set cycles 10
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0004
check reg d0 = 0x00000000
done

# test LSR.L
start lsr.l #1, d0 (0xe288), take 2
set mem 0x002000 = 0xe288
set reg d0 = 0x55aaaa55
set pc 0x002000
set cycles 10
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0011
check reg d0 = 0x2ad5552a
done

# test LSR.L
start lsr.l #2, d0 (0xe488), take 1
set mem 0x002000 = 0xe488
set reg d0 = 0x55aaaa54
set pc 0x002000
set cycles 12
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0000
check reg d0 = 0x156aaa95
done

#
# Test ASR instruction (ASR.B)
#

# test ASR.B
start asr.b #1, d0 (0xe200), take 1
set mem 0x002000 = 0xe200
set reg d0 = 0x55aa5500
set pc 0x002000
set cycles 8
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0004
check reg d0 = 0x55aa5500
done

# test ASR.B
start asr.b #1, d0 (0xe200), take 2
set mem 0x002000 = 0xe200
set reg d0 = 0x55aa55a5
set pc 0x002000
set cycles 8
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0019
check reg d0 = 0x55aa55d2
done

# test ASR.B
start asr.b #2, d0 (0xe400), take 1
set mem 0x002000 = 0xe400
set reg d0 = 0x55aa55a5
set pc 0x002000
set cycles 10
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0008
check reg d0 = 0x55aa55e9
done

#
# Test ASR instruction (ASR.W)
#

# test ASR.W
start asr.w #1, d0 (0xe240), take 1
set mem 0x002000 = 0xe240
set reg d0 = 0x55aa0000
set pc 0x002000
set cycles 8
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0004
check reg d0 = 0x55aa0000
done

# test ASR.W
start asr.w #1, d0 (0xe240), take 2
set mem 0x002000 = 0xe240
set reg d0 = 0x55aaaa55
set pc 0x002000
set cycles 8
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0019
check reg d0 = 0x55aad52a
done

# test ASR.W
start asr.w #2, d0 (0xe440), take 1
set mem 0x002000 = 0xe440
set reg d0 = 0x55aaaa54
set pc 0x002000
set cycles 10
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0008
check reg d0 = 0x55aaea95
done

#
# Test ASR instruction (ASR.L)
#

# test ASR.L
start asr.l #1, d0 (0xe280), take 1
set mem 0x002000 = 0xe280
set reg d0 = 0x00000000
set pc 0x002000
set cycles 10
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0004
check reg d0 = 0x00000000
done

# test ASR.L
start asr.l #1, d0 (0xe280), take 2
set mem 0x002000 = 0xe280
set reg d0 = 0x55aaaa55
set pc 0x002000
set cycles 10
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0011
check reg d0 = 0x2ad5552a
done

# test ASR.L
start asr.l #2, d0 (0xe480), take 1
set mem 0x002000 = 0xe480
set reg d0 = 0xa5aaaa54
set pc 0x002000
set cycles 12
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0008
check reg d0 = 0xe96aaa95
done

#
# Test ROXL instruction (ROXL.B)
#

# test ROXL.B
start roxl.b #1, d0 (0xe310), take 1
set mem 0x002000 = 0xe310
set reg d0 = 0x55aa5500
set pc 0x002000
set cycles 8
set flags 0x000f
run
check cycles 0
check pc 0x002002
check flags 0x0004
check reg d0 = 0x55aa5500
done

# test ROXL.B
start roxl.b #1, d0 (0xe310), take 2
set mem 0x002000 = 0xe310
set reg d0 = 0x55aa55aa
set pc 0x002000
set cycles 8
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0011
check reg d0 = 0x55aa5554
done

# test ROXL.B
start roxl.b #2, d0 (0xe510), take 1
set mem 0x002000 = 0xe510
set reg d0 = 0x55aa55aa
set pc 0x002000
set cycles 10
set flags 0x0010
run
check cycles 0
check pc 0x002002
check flags 0x0008
check reg d0 = 0x55aa55ab
done

# test ROXL.B
start roxl.b d1, d0 (0xe330), take 1
set mem 0x002000 = 0xe330
set reg d0 = 0x55aa55aa
set reg d1 = 0
set pc 0x002000
set cycles 6
set flags 0x0010
run
check cycles 0
check pc 0x002002
check flags 0x0019
check reg d0 = 0x55aa55aa
done

# test ROXL.B
start roxl.b d1, d0 (0xe330), take 2
set mem 0x002000 = 0xe330
set reg d0 = 0x55aa55aa
set reg d1 = 2
set pc 0x002000
set cycles 10
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0008
check reg d0 = 0x55aa55a9
done

#
# Test ROXL instruction (ROXL.W)
#

# test ROXL.W
start roxl.w #1, d0 (0xe350), take 1
set mem 0x002000 = 0xe350
set reg d0 = 0x55aa0000
set pc 0x002000
set cycles 8
set flags 0x000f
run
check cycles 0
check pc 0x002002
check flags 0x0004
check reg d0 = 0x55aa0000
done

# test ROXL.W
start roxl.w #1, d0 (0xe350), take 2
set mem 0x002000 = 0xe350
set reg d0 = 0x55aaaa55
set pc 0x002000
set cycles 8
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0011
check reg d0 = 0x55aa54aa
done

# test ROXL.W
start roxl.w #2, d0 (0xe550), take 1
set mem 0x002000 = 0xe550
set reg d0 = 0x55aaaa55
set pc 0x002000
set cycles 10
set flags 0x0010
run
check cycles 0
check pc 0x002002
check flags 0x0008
check reg d0 = 0x55aaa957
done

# test ROXL.W
start roxl.w d1, d0 (0xe370), take 1
set mem 0x002000 = 0xe370
set reg d0 = 0x55aa55aa
set reg d1 = 0
set pc 0x002000
set cycles 6
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0011
check reg d0 = 0x55aa55aa
done

# test ROXL.W
start roxl.w d1, d0 (0xe370), take 2
set mem 0x002000 = 0xe370
set reg d0 = 0x55aa55aa
set reg d1 = 2
set pc 0x002000
set cycles 10
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0011
check reg d0 = 0x55aa56aa
done

#
# Test ROXL instruction (ROXL.L)
#

# test ROXL.L
start roxl.l #1, d0 (0xe390), take 1
set mem 0x002000 = 0xe390
set reg d0 = 0x00000000
set pc 0x002000
set cycles 10
set flags 0x000f
run
check cycles 0
check pc 0x002002
check flags 0x0004
check reg d0 = 0x00000000
done

# test ROXL.L
start roxl.l #1, d0 (0xe390), take 2
set mem 0x002000 = 0xe390
set reg d0 = 0xd5aaaa55
set pc 0x002000
set cycles 10
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0019
check reg d0 = 0xab5554aa
done

# test ROXL.L
start roxl.l #2, d0 (0xe590), take 1
set mem 0x002000 = 0xe590
set reg d0 = 0x15aaaa55
set pc 0x002000
set cycles 12
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0000
check reg d0 = 0x56aaa956
done

# test ROXL.L
start roxl.l d1, d0 (0xe3b0), take 1
set mem 0x002000 = 0xe3b0
set reg d0 = 0x55aa55aa
set reg d1 = 0
set pc 0x002000
set cycles 8
set flags 0x001f
run
check cycles 0
check pc 0x002002
check flags 0x0011
check reg d0 = 0x55aa55aa
done

# test ROXL.L
start roxl.l d1, d0 (0xe3b0), take 2
set mem 0x002000 = 0xe3b0
set reg d0 = 0x55aa55aa
set reg d1 = 2
set pc 0x002000
set cycles 12
set flags 0x0000
run
check cycles 0
check pc 0x002002
check flags 0x0011
check reg d0 = 0x56a956a8
done

#
# $Log$
#
